The present invention relates to semiconductor transistor fabrication and more particularly to complementary field effect transistors (CMOS) and integrated circuits containing them.
Integrated circuit technology continues to advance at a rapid pace, with many circuit technologies being implemented using semiconductor fabrication processes. With the advancement of semiconductor circuit fabrication methods, consideration is given to various aspects, including maximizing efficiency, lowering manufacturing cost, and increasing performance. With these goals in mind, one area is the continuing trend of reducing the thickness of the transistor gate dielectrics. For example, in the past the gate dielectric (e.g., silicon dioxide or nitrided silicon dioxide) layer thickness was on the order of 10 nm, but more recently that thickness has reduced considerably with a more current goal being on the order of 2 nm Indeed, this goal will strive for even thinner gate dielectric layers in the foreseeable future. This goal reduces device size and facilitates improved device performance.
While the desirability and trend toward thinner gate dielectrics continues, such an approach also provides a considerable drawback. Specifically, overlying the thin gate dielectric is a polycrystalline silicon (“polysilicon”) gate layer, and polysilicon naturally includes a depletion region at the interface between the polysilicon gate and the gate dielectric. Typically, the depletion region manifests itself as providing the electrical equivalent of approximately a 0.3 nm thick insulator and, as such, the region in effect provides an insulating effect rather than a conducting effect as would be present in the remainder of the polysilicon gate conductor. Using the preceding numeric example, therefore, for a 10-nm thick gate dielectric, then the overlying effective 0.3-nm thick polysilicon depletion region may be thought to effectively increase the overall insulation between the gate and the underlying transistor channel from 10 nm to 10.3 nm, that is, the effect of the depletion region affects the insulating thickness by three percent—as such, for previous thicker gate insulators the effect of the polysilicon depletion region may be considered to have a negligible impact on the gate dielectric. In contrast, however, for a 2-nm thick gate dielectric, the polysilicon gate conductor depletion region may be thought to increase the gate insulator to 2.3 nm, thereby representing an increase on the order of 15 percent. This increased percentage significantly reduces the benefits otherwise provided by the thinner gate dielectric.
One approach in general to avoiding the depletion region phenomenon of polysilicon transistor gates is to use metal as an alternative material for the transistor gate because metal does not present a considerable depletion region, if any. Prior to the more recent use of polysilicon gates, metal gates were fairly common. However, a previously-identified drawback of such metal gates, which indeed led to the avoidance of such metals in contemporary devices, is that each metal has a corresponding so-called work function, and in the transistor art each transistor also has a corresponding preferred value for a work function of the gate electrode. However, the desired work function value differs for different transistor types. For example, based on present day threshold voltage channel doping, a p-channel MOS transistor (“PMOS”) is optimized when the gate electrode has a work function on the order of 5 eV; while an n-channel MOS transistor (“NMOS”) is optimized when the gate electrode has a work function on the order of 4 eV. The problem with previously-used metal gates arose with the development of CMOS circuits which, by definition, include both PMOS and NMOS transistors. Specifically, because a metal gate provides only a single work function, then it could not be selected to provide the two different desired work functions of the PMOS and NMOS devices. Instead, at best a metal could be selected to be between the desired work function of a PMOS and an NMOS transistor, which is sometimes referred to as the “midgap” between these devices (i.e., on the order of 4.5 eV for the preceding examples). This inability to match different work functions led to the use of polysilicon gates whereby the polysilicon gates of the NMOS devices could be doped in a first manner in view of the desired work function for NMOS transistors and the polysilicon gates of the PMOS devices could be doped in a second manner in view of the desired work function for PMOS transistors.
More recent approaches have used two different metals for gates. For example, U.S. Pat. No. 6,265,258 deposits a tantalum metal gate layer (work function about 4.2 eV) and then selectively nitrides the portion over the PMOS areas to form tantalum nitride gates (work function about 5.4 eV) while the NMOS gates remain tantalum. Similarly, U.S. Pat. No. 6,204,103 deposits polysilicon and over the NMOS areas deposits titanium and over the PMOS areas deposits molybdenum; then an anneal simultaneously forms titanium silicide gates for NMOS and molybdenum silicide gates for PMOS. And Polishchuk et al, Dual Work Function Metal Gate CMOS Technology Using Metal Interdiffusion, 22 IEEE Elect. Dev. Lett. 444–446 (2001) describes forming two CMOS gates of two differing metals: Ti and a Ti:Ni mixture with the Ni segregating at the gate dielectric interface by diffusion of the Ni through the Ti. This provides gate work functions of about 3.9 (Ti) for the NMOS and about 5.3 (Ni) for the PMOS.
However, the foregoing two metal or silicide gate approaches have processing drawbacks including silicide interface discontinuities.